The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit including a resistance region formed on a substrate integrally with an active device and a fabrication process thereof.
Generally, semiconductor devices are provided in the form of a semiconductor integrated circuit in which active devices such as transistors are formed on a substrate monolithically together with passive devices including resistances and/or capacitances.
In the fabrication process of semiconductor integrated circuits, it is preferable that these passive devices are formed simultaneously with the active devices, without increasing the number of the fabrication steps. Further, it is preferable that the active devices are formed with minimum size for maximizing the operational speed thereof.
FIGS. 1A and 1B are diagrams showing the construction of a compound semiconductor integrated circuit device 10 of a related art in which a hetero-bipolar transistor (HBT) and a cooperating resistance element are integrated, wherein FIG. 1A shows the semiconductor integrated circuit in a plan view, while FIG. 1B shows the semiconductor integrated circuit in a cross-sectional view taken along a line 1-1xe2x80x2 of FIG. 1A.
Referring to the cross-sectional view of FIG. 1B, it can be seen that a semi-insulating GaAs substrate 11 is provided with a collector layer 11A of n-type GaAs, and a base layer 12 of thin p-type GaAs is formed epitaxially on the semi-insulating GaAs substrate 11. Further, an emitter layer 13 of n+-type GaInP is formed on the base layer 12 epitaxially.
The substrate 11 is divided into an active device region 10A and a resistance-element region 10B by a device-isolation trench 11B, wherein it can be seen that a device-isolation region 11C of high resistance is formed inside the device-isolation trench 11B by an ion implantation process. Thus, the device-isolation trench 11B thus formed defines the mesa structure for the active device region 10A and also the mesa structure for the resistance-element region 10B.
In the active device region 10A, it should be noted that the emitter layer 13 forms an emitter pattern of a reduced lateral size on the base layer 12 so as to minimize the base-emitter capacitance, and a ring-shaped base electrode 15A is formed on the surface of the base layer 12 thus exposed as represented in FIG. 1A. Further, an emitter electrode 14 is formed on the emitter pattern 13, wherein the emitter electrode 14 extends laterally as a result of the lateral etching process applied to the emitter pattern 13 for reducing the size, and hence the area, thereof. Thereby, the emitter electrode 14 forms an overhang structure on the emitter pattern 13.
On the resistance-element region 10B, on the other hand, electrodes 15C and 15D are formed on the same base layer 12. Thereby, there is formed a resistance element having a resistor body provided by the base layer 12 and the electrodes 15C and 15D as terminals. In the description hereinafter, the resistance element thus formed in the region 10B will be designated also by a numeral 10B. Similarly, the HBT formed on the active region 10A will be designated also by a numeral 10A.
In such a semiconductor integrated circuit of FIGS. 1A and 1B, it is preferable to form the resistance element and the active device simultaneously by a common process. Thus, there is proposed a process to form the base electrode 15A of the HBT 10A and the electrodes 15C and 15D of the resistance element 10B simultaneously.
In more detail, deposition of a conductive layer constituting the base electrode 15A is made on the active device region 10A while using the emitter electrode 14 as a mask, after the step of forming the emitter pattern 13 on the base layer 12 and after the step of forming the emitter electrode. As a result of the deposition of the conductive layer thus conducted while using the emitter electrode 14 as a self-alignment mask, an electrode pattern 15B of the same composition as the base electrode 15A is formed also on the emitter electrode 14.
As a result of the deposition of the conductive layer, the electrodes 15C and 15D are formed at the same time, as noted previously. In view of the fact that the electrodes 15C and 15D are used as the different terminals of the resistance element, it is necessary that the electrodes 15C and 15D are isolated from each other, and thus, it has been necessary to apply a patterning process using a mask for forming the electrodes 15C and 15D.
In view of the circumstances noted above, it has been necessary to use a mask having mask openings P1-P3 corresponding respectively to the electrode patterns 15A, 15C and 15D as represented in FIG. 2A for patterning the electrodes 15C and 15D, while no such a mask is actually needed for patterning the base electrode 15A. It should be noted that the emitter electrode 14 can be used as a self-aligned mask during the process of forming base electrode 15A of the HBT 10A.
In the fabrication process of the semiconductor integrated circuit 10 of the related art, it should be noted that another mask process, using a mask pattern having mask openings Q1 and Q2 respectively corresponding to the mesa region 10A and the mesa region 10B represented in FIG. 2B, is necessary for forming the device isolation trench 11B.
Thus, the fabrication process of the semiconductor integrated circuit 10 of the related art includes two different mask processes, one using the mask pattern of FIG. 2A for forming the electrodes 15A, 15C and 15D, and the other using the mask pattern of FIG. 2B for forming the mesa regions 10A and 10B.
In such a process that uses two different mask processes, there inevitably arises the problem of mask misalignment. Thus, in order to tolerate possible mask misalignment, it has been necessary to secure a sufficiently large area for the mesa regions 10A and 10B, while such an increase of the mesa area invites unwanted increase of parasitic capacitance and resultant decrease of the operational speed of the HBT. In FIGS. 1A and 1B it should be noted that the drawings represent resist patterns 16A and 16B that are formed by the mask pattern of FIG. 2B, wherein the resist pattern 16A corresponds to the resist opening Q1 while the resist pattern 16B corresponds to the resist opening Q2.
The foregoing problem of increased parasitic capacitance of HBT may be eliminated when a self-alignment mask similar to that used for the active device region 10A is provided also in the resistance-element region 10B and make the electrodes 15C and 15D separate as a result of use of such a self-alignment mask. In this case, the mask process for patterning the electrodes 15C and 15D by using the mask of FIG. 2A can be omitted. Thus, when successful, such a process would minimize the area of the HBT 10A and simultaneously simplify the fabrication process of the semiconductor integrated circuit 10.
FIGS. 3A-3C represents the case of fabricating a semiconductor integrated circuit device by using a self-alignment mask also in the resistance-element region 10B according to the foregoing approach. It should be noted that FIGS. 3A-3C merely represent one possible option of eliminating the problem pertinent to the fabrication process of the semiconductor integrated circuit 10 of FIGS. 1A and 1B and does not represent a known or prior art process. In FIGS. 3A-3C, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 3A and 3B, it can be seen that the resistance-element region 10B of the semiconductor integrated circuit 10 now includes a dummy emitter region 13A having a reduced lateral size, and a dummy-emitter electrode 14A corresponding to the emitter electrode 14 is formed on the dummy emitter region 13A so as to form an overhang structure.
According to the process of FIGS. 3A and 3B, a conductive layer is deposited on the base layer 12 in correspondence to the resistance-element region 10B simultaneously to the step of forming the base electrode 15A of the HBT 10A, while using the dummy-emitter electrode 14A as a self-alignment mask. As a result of use of the self-alignment mask 14A, the deposited conductive layer form the electrode 15C at one side of the mask 14A and the electrode 15D at the other side of the mask 14A. In order to assume separation of the electrodes 15C and 15D from each other, the dummy-emitter electrode 14A is formed to have a width slightly larger than the width of the electrodes 15C or 15D. Associated with the formation of the electrodes 15C and 15D, a dummy electrode pattern 15E having a substantially identical composition with the electrodes 15C and 15D is formed on the dummy-emitter electrode 14A.
After formation of the base electrode 15A and the terminal electrodes 15C and 15D, the mesa regions 10A and 10B are formed by an ion milling process or a dry etching process while using a resist mask including resist patterns Q1 and Q2 respectively in correspondence to the mesa regions 10A and 10B as represented in FIG. 3C.
According to such an approach, it is no longer necessary to use two masks in two separate steps and the area of the active device region 10A for the HBT should be minimized.
However, the semiconductor integrated circuit thus formed by the process of FIGS. 3A and 3B has a serious problem of a conductive pattern 15X which may be formed so as to surround the mesa region 10B as represented in FIGS. 4A-4C associated with the patterning step of forming the mesa region for the resistance-element region 10B. Thus, there is a substantial risk in such a semiconductor integrated circuit that the resistance element cause short-circuit. In FIGS. 4A-4C, it should be noted that those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. In the drawings, it should be noted that FIG. 4A represents the resistance-element region 10B in a plan view while FIG. 4B represents the same resistance-element region 10B in a cross-sectional view taken along a line A-Axe2x80x2 in FIG. 4A. Further, FIG. 4C represents the resistance-element region 10B in a cross-sectional view taken along a line B-Bxe2x80x2 represented in FIG. 4C.
Referring to FIGS. 4A-4C. it should be noted that the mesa patterning process using the resist pattern 16B may cut a part of the electrode patterns 15C and 15D as represented in FIG. 4B. In such a case, the conductive pattern 15X can be formed on the sidewall of the mesa structure 10B as a patterning residue as represented in FIGS. 4A and 4C. As noted previously, such a patterning residue 15X can cause the problem of short-circuit of the electrodes 15C and 15D.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor integrated circuit wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor integrated circuit device having an active device and a resistance element formed monolithically on a substrate wherein the area of the active device is minimized and the risk of short-circuit of the resistance element is eliminated at the same time.
Another object of the present invention is to provide a semiconductor integrated circuit device, comprising:
a substrate carrying thereon an epitaxial layer;
a resistance element formed on a first region of said epitaxial layer; and
an active device formed on a second region of said epitaxial layer,
said first and second regions comprising first and second mesa regions respectively,
said first region carrying at least a first electrode defined by first and second, mutually opposing sidewalls and a second electrode defined by third and fourth, mutually opposing sidewalls,
said first and second sidewalls of said first electrode being in a relationship with respect to a sidewall of said first mesa region such that each of said first and second sidewalls is offset away from a hypothetical extension of said sidewall of said first mesa region in an inward direction of said first mesa region,
said fourth sidewall of said second electrode being in a flush relationship with said sidewall of said first mesa region.
Another object of the present invention is to provide a semiconductor integrated circuit device, comprising:
a substrate carrying thereon an epitaxial layer;
a resistance element formed on a first region of said epitaxial layer;
an active device formed on a second region of said epitaxial layer, said first and second regions comprising first and second mesa regions respectively;
a dummy pattern provided over said first mesa region such that said dummy pattern includes therein one or more openings with a separation from a mesa sidewall defining said first mesa structure;
a first electrode provided on said epitaxial layer in correspondence to said opening; and
a second electrode provided on said epitaxial layer outside of said dummy pattern.
Another object of the present invention is to provide a semiconductor integrated circuit device, comprising:
a substrate carrying thereon an epitaxial layer;
a resistance element formed on a first region of said epitaxial layer;
an active device formed on a second region of said epitaxial layer, said first and second regions comprising first and second mesa regions respectively;
a dummy pattern provided over said first mesa region such that said dummy pattern extends across a lateral boundary of said first mesa region at one or more locations;
a first electrode provided on said first mesa region at a first side of said dummy pattern; and
a second electrode provided on said first mesa region at a second, opposite side of said dummy pattern,
said dummy pattern forming a closed ring-shaped pattern.
Another object of the present invention is to provide a method of fabricating a semiconductor integrated circuit device, comprising the steps of:
forming a semiconductor layer and a first metal layer consecutively on a base layer formed epitaxially on a substrate;
patterning said first metal layer and said semiconductor layer consecutively to form a bipolar transistor in a first region of said base layer and a dummy pattern on a second region of said base layer, such that said bipolar transistor comprises an emitter layer formed from said semiconductor layer and an emitter electrode formed from said metal layer and such that said dummy pattern comprises a dummy emitter layer formed from said semiconductor layer and a dummy emitter electrode formed from said metal layer;
depositing a second metal layer on said base layer so as to cover said first and second regions while using said emitter electrode in said first region as a self-alignment mask and using said dummy emitter electrode in said second region as a self-alignment mask; and
forming a first mesa structure in said first region and a second mesa structure in said second region while using a mask having a first mask opening corresponding to said first region and a second mask opening corresponding to said second region.
According to the present invention, it is possible to form at least one of the electrodes constituting a terminal of a resistance element in a resistance-element region in such a manner that the electrode is offset away from the sidewall surface of the mesa structure that provides the resistance-element region. In such a construction, the problem of short circuit of the resistance element is positively eliminated even in such a case in which a patterning residue remains on the mesa sidewall surface at the time of self-aligned patterning process of the electrodes of the resistance terminals, which is conducted by using a dummy pattern as a self-alignment mask. The process of forming such a dummy pattern can be conducted simultaneously to the process of forming an emitter electrode. Thus, the process of the present invention can avoid extraneous process steps.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.